In computing applications, a processing system is often designed to meet a specific application, such that cost, speed, power consumption, heat dissipation, and other design factors of the processing system are optimized. However, increased demands for performance of the processing system would often require additional resources that have not been designed into the processing system. Redesigning the processing system often requires substantial chip redesigns and verification schemes that require long design cycle times and new “pinouts.” Depending on the complexity of the changes, the time-to-market of a new design may result in being late (or even missing) a target market window for the new processing system.
The problems noted above are solved in large part by a die expansion bus that efficiently couples a custom portion of a design to an original portion of the design. The disclosed die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing the memory endpoints associated with the bus subsystems of the supplemental portion of the processing system.